Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2025.1.0.39.0
Mon Feb 9 14:24:10 2026
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2025 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 3 -hsp m -pwrprd -html -rpt LED_impl_1.twr LED_impl_1.udb -gui -msgset D:/Avant_E70_Development_Board/test_project/Blinking Lights_QSPI/LED/promote.xml
------------------------------
Design: led
Family: LAV-AT
Device: LAV-AT-E70
Package: LFG1156
Performance: 3
Package Status: Preliminary Version 7
Performance Hardware Data Status : Preliminary Version 105.1
------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
2 Setup at Speed Grade 3 Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 3 Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
Operating conditions:
--------------------
ldc_set_vcc -bank 1 3.3
Bank 1 voltage: 3.3 V
ldc_set_vcc -bank 2 3.3
Bank 2 voltage: 3.3 V
ldc_set_vcc -bank 0 3.3
Bank 0 voltage: 3.3 V
ldc_set_vcc -bank 3 1.8
Bank 3 voltage: 1.8 V
ldc_set_vcc -bank 4 1.8
Bank 4 voltage: 1.8 V
ldc_set_vcc -bank 5 1.8
Bank 5 voltage: 1.8 V
ldc_set_vcc -bank 6 1.8
Bank 6 voltage: 1.8 V
ldc_set_vcc -bank 7 1.8
Bank 7 voltage: 1.8 V
ldc_set_vcc -bank 8 1.8
Bank 8 voltage: 1.8 V
ldc_set_vcc -bank 9 1.1
Bank 9 voltage: 1.1 V
ldc_set_vcc -bank 10 1.1
Bank 10 voltage: 1.1 V
ldc_set_vcc -bank 11 1.1
Bank 11 voltage: 1.1 V
ldc_set_vcc -bank 12 3.3
Bank 12 voltage: 3.3 V
ldc_set_vcc -bank 13 3.3
Bank 13 voltage: 3.3 V
ldc_set_vcc -bank 14 3.3
Bank 14 voltage: 3.3 V
1.2 Constraint Coverage
Constraint Coverage: 0%
1.3 Overall Summary
Setup at Speed Grade 3 Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Setup at Speed Grade 3 Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
--------------------------------------------------
There is no start point satisfying reporting criteria
Clocked but unconstrained timing end points
--------------------------------------------------
There is no end point satisfying reporting criteria
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 10 Start or End Points | Type
-------------------------------------------------------------------
osc_clk | input
rst | input
LED_0[0] | output
LED_0[1] | output
LED_0[2] | output
LED_0[3] | output
LED_0[4] | output
LED_0[5] | output
LED_0[6] | output
LED_0[7] | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 18
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
-------------------------------------------------------------------
Listing 1 Net(s) | Source pin
-------------------------------------------------------------------
osc_clk_c[0] | osc_clk_ibuf.bb_inst/O
-------------------------------------------------------------------
|
Number of clock nets without clock defi |
nition | 1
|
-------------------------------------------------------------------
1.5 Combinational Loop
None
2 Setup at Speed Grade 3 Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
--------------------------------------------------
There is no end point satisfying reporting criteria
Total Negative Slack: 0
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 3 Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
--------------------------------------------------
There is no end point satisfying reporting criteria
Total Negative Slack: 0
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
--------------------------------------------------
There is no end point satisfying reporting criteria
Total Negative Slack: 0
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################